1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to field effect transistors and manufacturing techniques, in which an embedded strain-inducing semiconductor material is used for performance enhancement of the transistors.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies for advanced semiconductor devices are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips, graphic devices and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially determines the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
On the other hand, the continuous shrinkage of the gate length of planar transistor configurations may typically result in very sophisticated topographical configurations, since the gate height may not be proportionally reduced in relation to the gate length, unless very complicated process strategies are used for maintaining the desired overall gate conductivity and the ion blocking effect during the formation of drain and source regions of the transistors in which the gate electrode, in combination with a spacer structure, typically acts as an implantation mask. Consequently, upon further reducing the gate length in order to improve performance of the individual transistors and also increase overall packing density of the semiconductor devices, the space between neighboring gate electrode structures may also be reduced. In advanced approaches, the performance of closely spaced transistors may, however, strongly depend on the overall manufacturing strategy, in particular when additional performance enhancing mechanisms are implemented in one or both types of transistors. For example, for a given gate length of field effect transistors, the performance thereof may be further increased by inducing a certain type of strain in the channel region of the transistors, which may have a strong effect on the resulting charge carrier mobility. For a standard crystallographic configuration, a compressive strain component in the channel region of P-channel transistors may significantly enhance the overall drive current capability due to an increase of the mobility of holes, which represent the dominant charge carriers in P-channel transistors. Similarly, a tensile strain component in N-channel transistors may result in a significant increase of electron mobility, thereby also improving the drive current capability. One efficient mechanism for increasing the strain locally in P-channel transistors is the incorporation of a strain-inducing semiconductor alloy, such as a silicon/germanium alloy, which may result in a significant compressive strain component. For this purpose, cavities may be selectively formed in the active regions of the P-channel transistors after the patterning of the basic gate electrode structures and the cavities may be refilled with a crystalline silicon/germanium alloy, which may be grown on the remaining silicon base material, thereby obtaining the desired compressive strained state.
These sophisticated strain-inducing mechanisms may enable forming transistors of reduced dimensions, while, nevertheless, preserving a certain minimum thickness of the silicon dioxide based gate dielectric material in order to keep the resulting leakage currents at an acceptable level. It is well known that reducing, for instance, the gate length of field effect transistors may be associated with the requirement of increasing the capacitive coupling of the gate electrode to the channel region in order to provide an appropriate controllability of the current flow in the channel region. Typically, the increased capacitive coupling may be accomplished by reducing the thickness of the gate dielectric material, which is typically provided in the form of a silicon dioxide based material due to the superior characteristics of a silicon dioxide/silicon interface.
Recently, a plurality of process strategies and device architectures have been proposed in an attempt to replace the well-established silicon dioxide based gate dielectric material with sophisticated material systems, which have a high dielectric constant and, thus, provide superior capacitive coupling for a given physical layer thickness. Although many of these approaches may represent promising strategies, nevertheless, providing transistors on the basis of efficient internal strain-inducing mechanisms still provides the possibility of forming powerful semiconductor devices including field effect transistors having critical dimensions of 50 nm and less, while, however, avoiding the incorporation of very complex material systems and process strategies, as are typically associated with the introduction of high-k dielectric materials in combination with metal-containing electrode materials.
Although, for instance, the incorporation of a strain-inducing silicon/germanium alloy in the active region of P-channel transistors is a very efficient strategy for enhancing drive current and switching speed of the P-channel transistors, significant variations of transistor characteristics have been observed in sophisticated semiconductor devices. For example, the drive current of P-channel transistors, which have incorporated therein a strain-inducing silicon/germanium alloy, may exhibit significant variations across single die areas, wherein, in particular, significant differences may exist between very dense device areas and areas of reduced packing density. Typically, in complex semiconductor devices, a plurality of circuit portions may have to interact with each other, wherein the various operating speeds may have to be matched to each other in order to provide a proper functional behavior of the total circuitry. For this reason, the operating conditions of certain circuit portions may have to be adjusted so as to work at reduced performance in order to match the operating capabilities of other device portions, thereby providing, in total, a semiconductor device of reduced performance. Consequently, improving uniformity of drive current capabilities of, in particular, P-channel transistors would provide superior conditions upon targeting complex integrated circuits and generally classifying the finished semiconductor devices. Further-more, in addition to a significant variation of the saturation currents of P-channel transistors, a pronounced variation of the threshold voltage has also been observed across semiconductor dies, which may also result in a significantly reduced number of high performance devices for a given product technology and process strategy.
With reference to FIGS. 1a-1b, a typical process strategy and semiconductor devices including P-channel transistors having incorporated therein a strain-inducing silicon/germanium alloy will be described in more detail, in order to identify critical process stages.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 and a semiconductor layer 102, which typically represents a silicon-based semiconductor material, at least in an initial state, prior to forming circuit elements in the semiconductor layer 102. The semiconductor device 100 may represent a silicon-on-insulator (SOI) device, in which a buried insulating layer (not shown) may be formed between the substrate 101 and the semiconductor layer 102. In other cases, the silicon-based semiconductor layer 102 is a part of a crystalline semiconductor material of the substrate 101 and may represent a “bulk” configuration. In the manufacturing stage shown, a shallow trench isolation region or structure 110 is formed in the semiconductor layer 102 and extends down to a specific depth, for instance several ten of nanometers, depending on the device requirements. In SOI architectures, the shallow trench isolation 110 typically extends down to the buried insulating layer. The isolation structure 110, thus, laterally delineates an active region 102A in the semiconductor layer 102 and, thus, defines the lateral size and position of the active region 102A. It should be appreciated that, typically, a plurality of active regions are provided in the device 100 on the basis of the isolation structure 110. To this end, the isolation structure 110 may comprise appropriately dimensioned isolation trenches, which may have a width of 100 nm and less, between two different active regions in densely packed device areas, while, in other cases, trenches having a width of several hundred nanometers and more may be provided in the structure 110, for instance when requiring extended isolation regions and the like. The trench isolation 110 may be comprised of silicon dioxide material, which is a well-established dielectric material in semiconductor devices due to the superior interface characteristics of silicon dioxide and silicon, as discussed above.
In the example shown in FIG. 1a, the active region 102A, which may be understood as a semiconductor region having formed therein or receiving PN junctions for at least one transistor element, comprises drain and source regions 152 of a plurality of transistors 150, which represent P-channel transistors in the example shown. Moreover, as previously discussed, strain-inducing silicon/germanium regions 151 may be provided in the active region 102A laterally adjacent to gate electrode structures 155 in order to induce uniaxial strain in channel regions 153, thereby significantly increasing charge carrier mobility in the channel regions 153, which may, thus, provide superior drive current and switching speed of the transistors 150. Moreover, in the manufacturing stage shown, the gate electrode structures 155, which may comprise a gate dielectric material 155A, for instance in the form of a silicon dioxide based material, such as a nitrogen-enriched silicon dioxide material, and a polysilicon material 155B, may have formed on sidewalls thereof a spacer structure 154. As previously discussed, the gate electrode structures 155 may have a length, i.e., in FIG. 1a, the horizontal direction, which also represents the current flow direction in the channel regions 153, of 50 nm and less, which may generally provide fast and powerful semiconductor devices on the basis of conventional materials, such as silicon dioxide based gate dielectrics and a polysilicon electrode material for the gate electrode structures 155.
FIG. 1b schematically illustrates the semiconductor device 100, wherein transistors 150 may be provided in active regions 102B, 102C, which may have a reduced length compared to the active region 102A as shown in FIG. 1a. Consequently, in this case, a reduced number of transistors may be provided in each of the active regions 102B, 102C, while, on the other hand, the overall basic configurations of the transistors 150 may be identical for the active regions 102A, 102B and 102C.
The semiconductor device 100 as shown in FIGS. 1a and 1b may be formed on the basis of the following process techniques. The shallow trench isolation 110 may be formed in the semiconductor layer 102 by applying sophisticated lithography techniques in order to form an etch mask, which may then be used for patterning the semiconductor layer 102 so as to form appropriate trenches therein, in accordance with requirements for the lateral configuration of the isolation structure 110. Thereafter, silicon dioxide material may be deposited so as to refill the trenches, and any excess material may be removed by chemical mechanical polishing (CMP), followed by the removal of the etch mask. Thereafter, a plurality of well implantation processes may be performed on the basis of an appropriate masking regime in order to incorporate a dopant species for adjusting the basic characteristics of the transistors 150, for instance in terms of threshold voltage and the like. For example, typically, different threshold voltages may be required for basically the same transistor configuration, which may require two or more implantation steps so as to obtain different “flavors” of the same transistor type. Next, the gate electrode structures 155 are formed by providing the gate dielectric material 155A and the electrode material 155B in combination with a dielectric cap material and any further materials, such as hard mask materials, and the like, which are then patterned in accordance with the design rules of the device 100 based on sophisticated lithography and etch techniques. Thereafter, an appropriate spacer structure may be provided so as to form cavities in the active region 102A, while any other active regions may be covered by a mask material, which may also act as an appropriate mask during the refilling of the cavities by means of a selective epitaxial growth process for providing the silicon/germanium material 151. Next, the drain and source regions 152 in combination with the spacer structure 154 may be formed on the basis of any appropriate process technique, followed by any anneal processes in order to adjust the final dopant profile of the drain and source regions 152.
Upon operating the device 100, it has been observed that the transistor characteristics may vary across the semiconductor device 100 and may even vary within individual active regions, such as the active region 102A as shown in FIG. 1a. For example, it has been recognized that transistors positioned immediately at the shallow trench isolation 110 may have a reduced performance compared to transistors which are not laterally adjacent to the isolation structure 110. Similarly, in total, the transistors 150 of FIG. 1b, which may be provided on the basis of the active regions 102C, 102B having a reduced length, may have a reduced performance compared to the entirety of the transistors 150 in the active region 102A. Thus, although the silicon/germanium alloy 151 may provide, in principle, superior transistor performance, the incorporation of the material 151 may also result in significant performance variations across the entire device and also within individual device areas, for instance with respect to transistors being positioned adjacent to a shallow trench isolation and transistors that are not positioned adjacent to a trench isolation region.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.